Advances in the field of interconnect and device technology has, over the years, played an important role in allowing continued scaling of microelectronic products. However, the increasing parasitic resistance in the nanometer regime increasingly degrades the high performance of these devices. Beyond the 32 nm Technology Node, predictions show the middle of the line (MOL) interconnection parasitic resistance contributor will become a key issue due to its high resistance. At the 32 nm and beyond technology nodes innovative solutions based on new materials and new processes have to be implemented to decrease the MOL total plug resistance. Electroplated Rh metallurgy has shown to be a promising alternative MOL technology to replace high resistivity chemical vapor deposition (CVD) tungsten (W) for 32 nm technology and beyond (I. Shao et al., IEEE proceedings of the 2007 International Interconnect Technology Conference (IITC), p 102-104 (2007). Electroplating of Rhodium (Rh) is demonstrated to have a robust process window, extendibility to 32 nm CMOS technology node and beyond, and a lower MOL resistance as compared to CVD W metallurgy. Iwasaki et al., (U.S. Publication No. 2002/0053741) describes a semiconductor device that may contain Rh (FIG. 7) layers on either side of a Cu layer. This construction reportedly gives a low resistivity interconnect. However, we discovered that, when put in direct contact, Rh and Cu diffuse into each other and this diffusion dramatically increases the resistivity of both a Rh seed and Cu line.